1. Field of the Invention
The invention relates generally to a multilayer microelectronic module and a method for making such a module. Specifically, the invention relates to a three-dimensional module comprised of electrically interconnected layers wherein at least one layer of which incorporates a thin small outline package (TSOP) that has been modified to have a surface area of an industry-standard (e.g., JEDEC) BGA package. Each TSOP layer may optionally be thinned so as to minimize the vertical height of the stack.
2. Description of the Prior Art
The demand for computer memory in the form of ball grid array packages (BGA) is increasing due greater memory capacity and speed available in such packages and to the smaller form factor or “foot print” of the BGA format.
BGA packages utilize solder ball interconnects on the underside of the package to interconnect the power and I/O from the semiconductor die within the package to external electronic circuitry. BGA packages therefore do not require the use of external outwardly projecting leads for interconnection as do TSOPs, so applications where small form factor is desirable tend to utilize BGA packages.
Further, computer memory manufactures are increasingly offering newer, more expensive, memory products only in a BGA format. This, in turn, results in end product manufactures, such as DIMM or server manufactures designing printed circuit boards and electronic assemblies such that only BGA memory packages can be used in or on the end product.
The previous generation of memory packaging technologies incorporated memory IC chips into a thin small outline package referred to as a TSOP. Because the TSOP packaging technology and manufacturing processes are mature, the TSOP memory product family tends to be well qualified, low cost and readily available.
To enhance TSOP memory circuit density, industry has taken advantage the ability to vertically stack and interconnect two or more layers containing TSOP or other microelectronic circuitry, to form high density, three-dimensional modules. The stacking of TSOP memory packages is known in the art as is reflected by U.S. patents issued to Irvine Sensors Corporation, assignee herein, such as U.S. Pat. No. 6,026,352 to Eide, U.S. Pat. No. 6,806,559, to Gann, et al., or U.S. Pat. No. 6,706,971 to Albert, et al., each of which is fully incorporated herein by reference.
With respect to stacking BGA packages, the available BGA packages are both expensive and have unique internal and external design characteristics and thermal issues that do not readily lend themselves to thinning, stacking and interconnecting. On the other hand, TSOPs are readily available, easily thinned and are relatively low in cost, but lack the standard BGA form factor desired by industry.
The present invention combines certain of the benefits available in both packages by providing a BGA scale stack comprised of at least one modified, thinned or unthinned TSOP layer.